Memory is designed and equipped in various electronic devices where DDR SDRAM is a kind of DRAM that can support double data rate i.e., transferring data on both the rising and falling edges of the DQ data strobe (DQS) signal to increase data rates. As the advance of technology, DDR SDRAM has been developed into DDR2 and DDR3 and even DDR4 where the data rates have been increased from 333/400 MHz of DDR to 800 MHz of DDR2, more than 1333 MHz of DDR3, or even higher data rates in the near future. As the increase of frequency, testers having high testing speed should be prepared to test the corresponding memory accordingly.
Testers such as T5503 provided by Advantest offer multiple DUTs (Device Under Test) parallel testing generate required testing patterns where testing fixtures have to be specially designed and implemented to access to DUTs through write and read operation. Normally, testing fixtures include test head, Hi-fix board for memory testing (load board/fixture board/DUT board/adopt board for logic device testing), and socket modules. Test head has different components such as drivers and comparators for signal driving and comparison. The Hi-Fix board has circuitry such as coaxial cables or circuitry of printed circuit boards for electrical connection between circuit modules and socket modules. The socket modules include a printed circuit board with a plurality of sockets to physically carry and electrically connect and test DUTs. Usually, Hi-Fix board and socket modules can be integrated as one single component.
The conventional DRAM memory has input pins and input/output (IO) pins where even with the similar input pin assignment, there are different IO pin configuration designs between x4 and x8 configuration.
Chih-Hui had disclosed an apparatus for universally testing semiconductor devices in U.S. Pat. No. 6,952,111 B1. According to the prior art patent, input pins do not need to consider signal output, therefore, the circuitry of testing fixtures can be simplified and designed as universal testing fixtures, i.e., a driver is implemented to control signal input of two DUTs as prior patent FIG. 3 (prior art) structure.
However, for input/output pins of memory with different I/O configurations, the existing solution is to prepare two sets of testing fixtures where each driver is electrically connected to input/output pins with the specific I/O configuration of a corresponding DUT with an exclusive circuitry as prior patent FIG. 5 (prior art) structure so that testing fixtures are interchanged according to different I/O configuration with different specifications which would greatly increase the capital investment of testers and reduce testing efficiency caused by interchanging of testing fixtures due to testing different I/O configuration. Furthermore, as prior patent FIGS. 6, 7 and 8 (prior art) structure, the revealed conventional testing device is electrically connected to input pins and I/O pins of Hi-Fix where the I/O pins of Hi-Fix are electrically interconnected to I/O pins of different device areas through a wiring bus then connected to drivers and comparators. Moreover, the I/O pins of DUTs in the untested device area are not connected.